A Theoretical Comparison Between Static - CMOS and Hybrid - RERL

This paper presents a theoretical comparison between a static-CMOS and a hybrid-RERL design of an inverter. The measurements taken into account are the total power dissipation, the performance in terms of propagation delay, and the size of each design. The hybrid-RERL architecture uses the RERL format except it reduces the 6-phase clock presented in earlier papers to a 5-phase clock by replacing the isolation switch on the output of the logic function with a non-gated, isolating device (i.e. a diode). Still, the hybrid-RERL logic makes further use of reversible logic. Although, the idea behind reversible logic (and adiabatic circuits) is to eliminate all non-adiabatic losses, this paper places a secondary goal of simplifying the hybrid-RERL inverter, which results in some non-adiabatic loss. Overall, the hybrid-RERL inverter significantly reduces power consumption at the cost of complexity and performance.